STANDARD COMPETENCIES:

 

 I.      Describe and draw planar capacitor structures. (I)

 II.     Describe how a BiCMOS circuit functions. (I)

 III.    Compare the difference between tensile and compressive stress.(I)

 IV.     Explain how purging reduces particle contamination. (I)

 V.      State the problems with native oxide growthl (I)

 VI.     Discuss proper behavior in the cleanroom. (I)

 VII.    Outline primary factors that impact die yield. (II)

 VIII.   Summarize  quality measures for Photo, Etch, Diffusion, Implant, Thinfilms and CMP. (II)

 IX.     Compute sheet resistance. (II)

 X       Assess resistance contour maps for uniformity. (II)

 XI.     Explain the C-V test. (II)

 XII.    Diagram a MOS gate with the following layers: EPI, wells, isolation, active, gate oxide, poly, source/drain, LDD, spacer, contact, plug, interconnect, via, and passivation. (III)

 XIII.   Describe overlay budget. (IV)

 XIV.    Contrast the difference between soft bake and hard bake. (IV)

 XV.     Construct a top view of a gate with shallow trench isolation, p & n wells, poly, source & drain implant, contact site, and metal wiring. (IV)

 XVI.    Compute values for resolution, wavelength, and numerical aperture (IV)

 XVII.   Outline common troubleshooting solutions for critical dimensions (IV)

 XVIII.  Compute selectivity. (V)

 XIX.    Discuss the primary operations for a Decoupled Plasma Source System. (V)

 XX      Breakdown the factors that affect plasma etch rate. (V)

 XXI.    Explain endpoint. (V)

 XXII.   Contrast the differences in function and construction between field oxide and gate oxide. (VI)

 XXIII.  Generalize the isolation methods for devices below .25um, and above .25um. (VI)

 XXIV.   Solve for dose, and beam current using the Dose formula. (VI)

 XXV.    Explain the primary difference between implants for wells, punch-through, and threshold voltage. (VI)

 XXVI.   Identify the three causes for dose uniformity problems. (VI)

 XXVII.  Discuss the primary operations for a High Density Plasma System. (VII)

 XXVIII. Examine the problem between interconnect delay and gate delay. (VII)

 XXIX.   Illustrate the three locations of particles associated with film deposition. (VII)

 XXX     Justify the use of barrier metals in processing. (VII)

 XXXI.   Summarize the primary process differences between Physical Vapor Deposition and Chemical Vapor Deposition. (VII)

 XXXII.  Solve for degree of planarization. (VIII)

 XXXIII. Analyze the various effects of Preston¿s equation on removal rate. (VIII)

 XXXIV.  Illustrate the differences between erosion and dishing. (VIII)

 XXXV.   Recommend process methods to correct non-uniform polishing. (VIII)

 XXXVI.  Explain the in-line parametric test. (IX)

 XXXVII. Illustrate the threshold voltage and drive current diagram. (IX)

 XXXVIII.Determine the causes for threshold voltage failure. (IX)

 XXXIX.  Construct the primary components of the Yield Management System. (IX)

 XL      List the five quality measures for wafer test. (IX)

 XLI.    Describe current developments in IC manufacturing. (X)

 TOPICAL OUTLINE:

 

 I.      Fundamental Technical Information

         A.      Device technology

         B.      Chemicals in Semiconductor Fabrication

         C.      Gas Control in Process Chambers (Delivery and Vacuum)

         D.      Contamination Control and Wafer Cleaning

 II.     Metrology and Defect Inspection

 III.    IC Fabrication Process Overview

 IV.     Photolithography

         A.      Vapor Prime and Softbake

         B.      Alignment and exposure

         C.      Advance Lithography

 V.      Removal

         A.      Wet Etch

         B.      Dry Etch

         C.      Strip

 VI.     Doping

         A.      Diffusion

         B.      Oxidation

         C.      Implant

 VII.    Thin Films

         A.      EPI

         B.      CVD

         C.      Metalization

 VIII.   Chemical Mechanical Polish

 IX.     Wafer Test

 X       Current Developments